1. Field of the Invention
The present invention relates to a power semiconductor device and a fabrication method thereof, and more particularly, to a power semiconductor device which has a high breakdown voltage structure using semi-insulating polycrystalline silicon, and a fabrication method thereof.
2. Description of the Related Art
With a recent trend toward large-sized and large capacity application apparatuses, a power semiconductor device having a high breakdown voltage, a high current capacity, and highspeed switching characteristics has become necessary.
A power semiconductor device requires a low saturation voltage, particularly, to reduce power loss in a conductive state while flowing a significant amount of current. Also, the power semiconductor device fundamentally requires high breakdown voltage characteristics, such as a property that the power semiconductor device can sustain a high reverse voltage applied to both ends of the power semiconductor device when or at the moment when a switch is turned off. The power semiconductor device requires various high breakdown voltages from tens to thousands of volts according to its application.
Meanwhile, the breakdown voltage of the semiconductor device is determined by a depletion region formed in a PN junction, since the voltage applied to the PN junction is mostly applied to the depletion region. It is known that the breakdown voltage is affected by the curvature of the depletion region. That is, in a planar junction, the electric field is concentrated more on an edge of a junction portion having a large curvature than on a flat portion thereof, due to an electric field crowding effect. Thus, an avalanche breakdown easily occurs at the edge, and the breakdown voltage of the entire depletion region is reduced.
Accordingly, several technologies have been proposed to prevent the concentration of the electric field on the edge of the junction portion. The first one is forming a field plate (FP) on a substrate of a field region adjacent to the edge of the planar junction. The second one is forming a field limiting ring (FLR), being an impurity layer having the same conductive type as the junction portion, in the substrate of the field region. The third one is combining the first and second technologies.
A method of forming a semi-insulating polycrystalline silicon (SIPOS) film on a substrate in which a planar junction is formed, which is introduced in an article published in the early 1970""s, has been continuously developed together with these technologies. The technology of manufacturing a high breakdown voltage semiconductor device using the SIPOS film can further reduce the area of a chip by about 10 to 20% compared to other technologies, and can obtain a stable breakdown voltage.
FIG. 1 is a cross-section of a high breakdown voltage transistor formed using a conventional SIPOS film.
Referring to FIG. 1, a base region 4 having a second conductivity type is formed on a collector region 2 having a first conductivity type, and an emitter region 6 having the first conductivity type is formed in the base region 4. A field limiting ring 8 for preventing an electric field from being concentrated on the edge of a junction between the collector region 2 and the base region 4 is formed a predetermined distance apart from the edge of the base region 4. A first conductive channel stop region 10 for isolation is formed in a field region spaced a predetermined distance apart from the field limiting ring 8.
In addition to the field limiting ring 8, An SIPOS film 12 for preventing concentration of the electric field on the edge of the junction, and an oxide film 14 are sequentially deposited on the semiconductor substrate. A base electrode 16, an emitter electrode 18, and an equipotential electrode 20 are formed, and a collector electrode 22 is formed on the bottom surface of the collector region 2.
At the xe2x80x9cThird International Symposium on Power Semiconductor Devices and ICsxe2x80x9d (in 1991), T. Stockmeler et al. applied and developed such a structure into a power diode structure which uses a technique for extending a junction edge portion instead of a field limiting ring, and uses a nitride film instead of an oxide film.
However, in such a structure, a remarkably large amount of reverse leakage current flows since the SIPOS film 12 is deposited directly on the semiconductor substrate. Thus, problems occur when actually applying this structure.
FIG. 2 is a cross-section of another power semiconductor device using a conventional SIPOS film. The same reference numerals as those in FIG. 1 denote the same elements, so they will not be described again.
Referring to FIG. 2, an oxide film 24 grown by thermal oxidation is first formed on a semiconductor substrate, and two SIPOS films 26 and 28 are deposited on the resultant structure. The first SIPOS film 26 on the oxide film 24 has an oxygen concentration of about 12% , and the second SIPOS film 28 has an oxygen concentration of about 25 to 30% . Thus, the surface is protected, and simultaneously a greater field plate effect can be provided than when the oxide film or nitride film is used.
However, when the SIPOS film is deposited in-situ twice, it is difficult to accurately control the thickness of the film or the concentration of oxygen. Therefore, determination of whether desired first and second SIPOS films are actually deposited is not possible during the process, thus difficult process management is expected. Also, the SIPOS film has a large scattering with respect to the high breakdown voltage, since it does not perform well under humid conditions. Furthermore, in the oxide film 24 deposited below the SIPOS film, the oxide film on the emitter region is 5,000 to 10,000 xc3x85 thick, the oxide film on the base region is 10,000 to 20,000 xc3x85 thick, and the oxide film on the field region is 15,000 to 30,000 xc3x85 thick. Thus, when the oxide film is dry etched in an etch process for forming a contact after forming the SIPOS film, the costs are high, and productivity of dry etch equipment is degraded.
It is an objective of the present invention to provide a power semiconductor device having improved characteristics by overcoming the above problems.
It is another objective of the present invention to provide a method for fabricating such a power semiconductor device.
Accordingly, to achieve the first objective, there is provided a power semiconductor device. The power semiconductor includes a collector region of a first conductivity type formed in a semiconductor substrate, a base region of a second conductivity type formed in the collector region, and an emitter region of the first conductivity type formed in the base region. A channel stop region is formed being spaced a predetermined distance from the base region. An insulative film, a semi-insulating polycrystalline silicon (SIPOS) film, and a nitride film patterned respectively to expose the emitter region, the base region, and the channel stop region are sequentially deposited on the semiconductor substrate. A base electrode, an emitter electrode, and an equipotential electrode are formed, which are connected respectively to the base region, the emitter region, and the channel stop region.
It is preferable that the insulative film on the emitter region is 500 to 5,000 xc3x85 thick, the insulating film on the base region is 1,000 to 10,000 xc3x85 thick, and the insulating film on a field region between the base region and the channel stop region is about 3,500 to 20,000 xc3x85 thick.
The nitride film is deposited by low pressure chemical vapor deposition (LP-CVD). The nitride film is preferably 500 to 5,000 xc3x85 thick. The base electrode extends a predetermined distance toward a field region. It is preferable that the nitride film and the SIPOS film each have a perpendicular sidewall, and the insulative film is isotropically etched to have an inclined sidewall.
To achieve the first objective, there is also provided another power semiconductor device. The device includes a cathode region having a first conductivity type formed in a semiconductor substrate, and an anode region having a second conductivity type formed in the cathode region. A channel stop region is spaced a predetermined distance from the anode region, in the cathode region. An insulative film, a SIPOS film, and a nitride film are sequentially deposited on the semiconductor substrate, which are patterned to expose parts of the anode region and the channel stop region. An anode electrode and an equipotential electrode are formed, which are connected respectively to the anode region and the channel stop region.
The insulative film on the channel stop region is preferably 500 to 5,000 xc3x85 thick, the insulative film on the anode region is preferably 1000 to 10,000 xc3x85 thick, and the insulative film on a field region between the anode region and the channel stop region is about 3,500 to 20,000 xc3x85 thick.
The nitride film is deposited by LP-CVD to a thickness of about 500 to 5,000 xc3x85.
To achieve the second objective, there is provided a method of fabricating a power semiconductor device. In this method, a collector region of a first conductivity type is formed in a semiconductor substrate. An insulative film for exposing a region of the semiconductor substrate in which a base region is to be formed, is formed on the semiconductor substrate in which the collector region is formed. A base region of a second conductivity type is formed in the collector region, and simultaneously an insulative film is formed on the entire surface of the resultant structure. A region of the semiconductor substrate in which an emitter region and a channel stop region are to be formed is exposed. An emitter region of the first conductivity type and a channel stop region are formed by implanting impurities into the semiconductor substrate, and simultaneously an insulative film is formed on the entire surface of the semiconductor substrate. After the insulative film is etched by a predetermined thickness, an SIPOS film and a nitride film are formed on the entire surface of the resultant structure. Parts of the base region, emitter region and channel stop region are exposed, and a base electrode, an emitter electrode, and an equipotential electrode connected respectively to the base region, the emitter region, and the channel stop region are then formed.
In the step of etching the insulative film to a predetermined thickness, it is preferable that the insulative film on the emitter region is 500 to 5,000 xc3x85 thick, the insulative film on the base region is 1,000 to 10,000 xc3x85 thick, and the insulative film on a field region between the base region and the channel stop region is about 3,500 to 20,000 xc3x85 thick.
Also, it is preferable that the SIPOS film and the nitride film are deposited by LP-CVD, and the nitride film is 500 to 5,000 xc3x85 thick.
In the step of exposing parts of the base region, emitter region, and channel stop region, the nitride film, the SIPOS film, and the insulative film are sequentially dry-etched.
To achieve the second objective, there is also provided another method of fabricating a power semiconductor device. In this method, a collector region of a first conductivity type is formed in a semiconductor substrate. An insulative film for exposing a region of the semiconductor substrate in which a base region is to be formed, is formed on the semiconductor substrate in which the collector region is formed. A base region of a second conductivity type is formed in the collector region, and simultaneously an insulative film is formed on the entire surface of the resultant structure. A region of the semiconductor substrate in which an emitter region and a channel stop region are to be formed is exposed. An emitter region of a first conductivity type and a channel stop region are formed by implanting impurities into the semiconductor substrate, and simultaneously an insulative film is formed on the entire surface of the semiconductor substrate. An SIPOS film and a nitride film are formed on the entire surface of the resultant structure, and the nitride film and the SIPOS film on the base region, the emitter region, and the channel stop region are then etched. A mask which exposes the insulative film on the base region, the emitter region and the channel stop region, is formed on the resultant structure. After the insulative is patterned using the mask, a base electrode, an emitter electrode, and an equipotential electrode connected respectively to the base region, the emitter region, and the channel stop region are formed.
Here, the nitride film and the SIPOS film are dry-etched, and the insulative film is wet-etched.
The SIPOS film and the nitride film are deposited by LP-CVD. Preferably, the nitride film is 500 to 5,000 xc3x85 thick.
It is preferable that the mask for exposing the insulative film has an aperture 2 to 5 xcexcm smaller than an aperture of the nitride film.